# Copyright 2022 Google LLC # # This source code is licensed under the BSD-style license found in the # LICENSE file in the root directory of this source tree. # # Description: microkernel filename lists for wasmsimd # # Auto-generated file. Do not edit! # Generator: tools/update-microkernels.py SET(PROD_WASMSIMD_MICROKERNEL_SRCS src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int16-u16.c src/f32-argmaxpool/f32-argmaxpool-4x-wasmsimd-c4.c src/f32-argmaxpool/f32-argmaxpool-9p8x-wasmsimd-c4.c src/f32-argmaxpool/f32-argmaxpool-9x-wasmsimd-c4.c src/f32-avgpool/f32-avgpool-9p8x-minmax-wasmsimd-arm-c4.c src/f32-avgpool/f32-avgpool-9p8x-minmax-wasmsimd-x86-c4.c src/f32-avgpool/f32-avgpool-9x-minmax-wasmsimd-arm-c4.c src/f32-avgpool/f32-avgpool-9x-minmax-wasmsimd-x86-c4.c src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x4-wasmsimd-2x2.c src/f32-dwconv/gen/f32-dwconv-3f3m3l4c4s4r-minmax-wasmsimd-arm.c src/f32-dwconv/gen/f32-dwconv-3f3m3l4c4s4r-wasmsimd.c src/f32-dwconv/gen/f32-dwconv-3f3m3l8c4s4r-minmax-wasmsimd-x86.c src/f32-dwconv/gen/f32-dwconv-3f3m3l8c4s4r-wasmsimd.c src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmsimd-arm.c src/f32-dwconv/gen/f32-dwconv-3p4c-wasmsimd.c src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmsimd-x86.c src/f32-dwconv/gen/f32-dwconv-3p8c-wasmsimd.c src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmsimd-arm.c src/f32-dwconv/gen/f32-dwconv-4p4c-wasmsimd.c src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmsimd-x86.c src/f32-dwconv/gen/f32-dwconv-4p8c-wasmsimd.c src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmsimd-arm.c src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-wasmsimd.c src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmsimd-arm.c src/f32-dwconv/gen/f32-dwconv-9p4c-wasmsimd.c src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-wasmsimd-x86.c src/f32-dwconv/gen/f32-dwconv-9p8c-wasmsimd.c src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-wasmsimd-arm.c src/f32-dwconv/gen/f32-dwconv-25p4c-wasmsimd.c src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-2x4.c src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-x86-loadsplat-2x4.c src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-arm-splat-1x4-acc4.c src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-wasmsimd-x86-splat-1x4-acc2.c src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-arm-splat-3x4.c src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-wasmsimd-x86-splat-3x4.c src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-arm-splat-1x4-acc2.c src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-wasmsimd-x86-splat-1x4-acc2.c src/f32-f16-vcvt/gen/f32-f16-vcvt-wasmsimd-u24.c src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmsimd-arm-splat.c src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmsimd-x86-loadsplat.c src/f32-gemm/gen/f32-gemm-1x8-minmax-wasmsimd-x86-splat.c src/f32-gemm/gen/f32-gemm-1x8-relu-wasmsimd-loadsplat.c src/f32-gemm/gen/f32-gemm-1x8-relu-wasmsimd-splat.c src/f32-gemm/gen/f32-gemm-1x8-wasmsimd-loadsplat.c src/f32-gemm/gen/f32-gemm-1x8-wasmsimd-splat.c src/f32-gemm/gen/f32-gemm-4x2c4-minmax-wasmsimd-arm.c src/f32-gemm/gen/f32-gemm-4x2c4-minmax-wasmsimd-x86.c src/f32-gemm/gen/f32-gemm-4x2c4-wasmsimd.c src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmsimd-x86-loadsplat.c src/f32-gemm/gen/f32-gemm-4x8-minmax-wasmsimd-x86-splat.c src/f32-gemm/gen/f32-gemm-4x8-relu-wasmsimd-loadsplat.c src/f32-gemm/gen/f32-gemm-4x8-relu-wasmsimd-splat.c src/f32-gemm/gen/f32-gemm-4x8-wasmsimd-loadsplat.c src/f32-gemm/gen/f32-gemm-4x8-wasmsimd-splat.c src/f32-gemm/gen/f32-gemm-5x8-minmax-wasmsimd-arm-splat.c src/f32-gemm/gen/f32-gemm-5x8-relu-wasmsimd-splat.c src/f32-gemm/gen/f32-gemm-5x8-wasmsimd-splat.c src/f32-ibilinear-chw/gen/f32-ibilinear-chw-wasmsimd-p8.c src/f32-ibilinear/gen/f32-ibilinear-wasmsimd-c8.c src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmsimd-arm-splat.c src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmsimd-x86-loadsplat.c src/f32-igemm/gen/f32-igemm-1x8-minmax-wasmsimd-x86-splat.c src/f32-igemm/gen/f32-igemm-1x8-relu-wasmsimd-loadsplat.c src/f32-igemm/gen/f32-igemm-1x8-relu-wasmsimd-splat.c src/f32-igemm/gen/f32-igemm-1x8-wasmsimd-loadsplat.c src/f32-igemm/gen/f32-igemm-1x8-wasmsimd-splat.c src/f32-igemm/gen/f32-igemm-4x2c4-minmax-wasmsimd-arm.c src/f32-igemm/gen/f32-igemm-4x2c4-minmax-wasmsimd-x86.c src/f32-igemm/gen/f32-igemm-4x2c4-wasmsimd.c src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmsimd-x86-loadsplat.c src/f32-igemm/gen/f32-igemm-4x8-minmax-wasmsimd-x86-splat.c src/f32-igemm/gen/f32-igemm-4x8-relu-wasmsimd-loadsplat.c src/f32-igemm/gen/f32-igemm-4x8-relu-wasmsimd-splat.c src/f32-igemm/gen/f32-igemm-4x8-wasmsimd-loadsplat.c src/f32-igemm/gen/f32-igemm-4x8-wasmsimd-splat.c src/f32-igemm/gen/f32-igemm-5x8-minmax-wasmsimd-arm-splat.c src/f32-igemm/gen/f32-igemm-5x8-relu-wasmsimd-splat.c src/f32-igemm/gen/f32-igemm-5x8-wasmsimd-splat.c src/f32-maxpool/f32-maxpool-9p8x-minmax-wasmsimd-arm-c4.c src/f32-maxpool/f32-maxpool-9p8x-minmax-wasmsimd-x86-c4.c src/f32-pavgpool/f32-pavgpool-9p8x-minmax-wasmsimd-arm-c4.c src/f32-pavgpool/f32-pavgpool-9p8x-minmax-wasmsimd-x86-c4.c src/f32-pavgpool/f32-pavgpool-9x-minmax-wasmsimd-arm-c4.c src/f32-pavgpool/f32-pavgpool-9x-minmax-wasmsimd-x86-c4.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmsimd-arm-splat.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-wasmsimd-x86-splat.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-relu-wasmsimd-splat.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-wasmsimd-splat.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmsimd-x86-splat.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-relu-wasmsimd-splat.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-wasmsimd-splat.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmsimd-arm-splat.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-relu-wasmsimd-splat.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-wasmsimd-splat.c src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasmsimd-magic-u32.c src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasmsimd-magic-u32.c src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmsimd-rr2-p5-u16-acc2.c src/f32-rdsum/gen/f32-rdsum-7p7x-minmax-wasmsimd-c16.c src/f32-rminmax/gen/f32-rmax-wasmsimd-pminmax-u16-acc4.c src/f32-rminmax/gen/f32-rminmax-wasmsimd-minmax-u16-acc4.c src/f32-rsum/gen/f32-rsum-wasmsimd-u16-acc4.c src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmsimd-arm.c src/f32-spmm/gen/f32-spmm-32x1-minmax-wasmsimd-x86.c src/f32-vbinary/gen/f32-vadd-wasmsimd-u16.c src/f32-vbinary/gen/f32-vaddc-wasmsimd-u16.c src/f32-vbinary/gen/f32-vdiv-wasmsimd-u16.c src/f32-vbinary/gen/f32-vdivc-wasmsimd-u16.c src/f32-vbinary/gen/f32-vmax-wasmsimd-arm-u16.c src/f32-vbinary/gen/f32-vmax-wasmsimd-x86-u16.c src/f32-vbinary/gen/f32-vmaxc-wasmsimd-arm-u16.c src/f32-vbinary/gen/f32-vmaxc-wasmsimd-x86-u16.c src/f32-vbinary/gen/f32-vmin-wasmsimd-arm-u16.c src/f32-vbinary/gen/f32-vmin-wasmsimd-x86-u16.c src/f32-vbinary/gen/f32-vminc-wasmsimd-arm-u16.c src/f32-vbinary/gen/f32-vminc-wasmsimd-x86-u16.c src/f32-vbinary/gen/f32-vmul-wasmsimd-u16.c src/f32-vbinary/gen/f32-vmulc-wasmsimd-u16.c src/f32-vbinary/gen/f32-vprelu-wasmsimd-u16.c src/f32-vbinary/gen/f32-vpreluc-wasmsimd-u16.c src/f32-vbinary/gen/f32-vrdivc-wasmsimd-u16.c src/f32-vbinary/gen/f32-vrpreluc-wasmsimd-u16.c src/f32-vbinary/gen/f32-vrsubc-wasmsimd-u16.c src/f32-vbinary/gen/f32-vsqrdiff-wasmsimd-u16.c src/f32-vbinary/gen/f32-vsqrdiffc-wasmsimd-u16.c src/f32-vbinary/gen/f32-vsub-wasmsimd-u16.c src/f32-vbinary/gen/f32-vsubc-wasmsimd-u16.c src/f32-vclamp/gen/f32-vclamp-wasmsimd-arm-u8.c src/f32-vclamp/gen/f32-vclamp-wasmsimd-x86-u8.c src/f32-vcmul/gen/f32-vcmul-wasmsimd-u8.c src/f32-vcopysign/gen/f32-vcopysign-wasmsimd.c src/f32-vcopysign/gen/f32-vcopysignc-wasmsimd.c src/f32-vcopysign/gen/f32-vrcopysignc-wasmsimd.c src/f32-velu/gen/f32-velu-wasmsimd-arm-rr2-p6-u16.c src/f32-velu/gen/f32-velu-wasmsimd-x86-rr2-p6-u16.c src/f32-vgelu/gen/f32-vgelu-wasmsimd-rational-12-10-div.c src/f32-vhswish/gen/f32-vhswish-wasmsimd-u16.c src/f32-vlog/gen/f32-vlog-wasmsimd-rational-3-3-div.c src/f32-vlrelu/gen/f32-vlrelu-wasmsimd-iminmax-u8.c src/f32-vlrelu/gen/f32-vlrelu-wasmsimd-laneselect-u8.c src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-wasmsimd-arm-2x.c src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-wasmsimd-x86-2x.c src/f32-vrelu/gen/f32-vrelu-wasmsimd-u16.c src/f32-vrnd/gen/f32-vrndd-wasmsimd-u8.c src/f32-vrnd/gen/f32-vrndne-wasmsimd-u8.c src/f32-vrnd/gen/f32-vrndu-wasmsimd-u8.c src/f32-vrnd/gen/f32-vrndz-wasmsimd-u8.c src/f32-vsigmoid/gen/f32-vsigmoid-wasmsimd-rr2-p5-div-u16.c src/f32-vsqrt/gen/f32-vsqrt-wasmsimd-sqrt-u8.c src/f32-vtanh/gen/f32-vtanh-wasmsimd-rational-9-8-div.c src/f32-vunary/gen/f32-vabs-wasmsimd.c src/f32-vunary/gen/f32-vneg-wasmsimd.c src/f32-vunary/gen/f32-vsqr-wasmsimd.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x4c8-minmax-wasmsimd-dot16x2-ld64.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x4c8-minmax-wasmsimd-dot16x2-ld64.c src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c2s4-minmax-wasmsimd-dot16x2-ld128.c src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c2s4-minmax-wasmsimd-dot16x2-ld128.c src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-1x4c2s4-minmax-wasmsimd-dot16x2-ld128.c src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-4x4c2s4-minmax-wasmsimd-dot16x2-ld128.c src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-wasmsimd-mul16-add16.c src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-wasmsimd-mul16-add16.c src/qs8-f32-vcvt/gen/qs8-f32-vcvt-wasmsimd-u32.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-wasmsimd-mul16-add16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-wasmsimd-mul16-add16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-wasmsimd-mul16-add16.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-rdsum/gen/qs8-rdsum-7p7x-wasmsimd-c32.c src/qs8-rsum/gen/qs8-rsum-wasmsimd-u32-acc4.c src/qs8-vadd/gen/qs8-vadd-minmax-wasmsimd-u32.c src/qs8-vaddc/gen/qs8-vaddc-minmax-wasmsimd-u32.c src/qs8-vcvt/gen/qs8-vcvt-wasmsimd-u16.c src/qs8-vlrelu/gen/qs8-vlrelu-wasmsimd-arm-u32.c src/qs8-vlrelu/gen/qs8-vlrelu-wasmsimd-x86-u16.c src/qs8-vmul/gen/qs8-vmul-minmax-fp32-wasmsimd-mul32-ld64-u8.c src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-wasmsimd-mul32-ld64-u8.c src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-wasmsimd-mul16.c src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-wasmsimd-mul16.c src/qu8-f32-vcvt/gen/qu8-f32-vcvt-wasmsimd-u32.c src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-rdsum/gen/qu8-rdsum-7p7x-wasmsimd-c32.c src/qu8-rsum/gen/qu8-rsum-wasmsimd-u32-acc4.c src/qu8-vadd/gen/qu8-vadd-minmax-wasmsimd-u32.c src/qu8-vaddc/gen/qu8-vaddc-minmax-wasmsimd-u32.c src/qu8-vcvt/gen/qu8-vcvt-wasmsimd-u16.c src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-arm-u32.c src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-x86-u16.c src/qu8-vmul/gen/qu8-vmul-minmax-fp32-wasmsimd-mul32-ld64-u8.c src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-wasmsimd-mul32-ld64-u8.c src/s8-ibilinear/gen/s8-ibilinear-wasmsimd-dot16x2-c8.c src/s8-maxpool/s8-maxpool-9p8x-minmax-wasmsimd-c16.c src/s8-vclamp/s8-vclamp-wasmsimd-u64.c src/s32-f32-vcvt/gen/s32-f32-vcvt-wasmsimd.c src/u8-ibilinear/gen/u8-ibilinear-wasmsimd-dot16x2-c8.c src/u8-maxpool/u8-maxpool-9p8x-minmax-wasmsimd-c16.c src/u8-vclamp/u8-vclamp-wasmsimd-u64.c src/x8-lut/gen/x8-lut-wasmsimd-u32.c src/x8-transposec/gen/x8-transposec-16x16-reuse-mov-wasmsimd.c src/x16-transposec/gen/x16-transposec-8x8-reuse-mov-wasmsimd.c src/x32-packw/gen/x32-packw-x2c4-gemm-goi-wasmsimd-u4.c src/x32-packw/gen/x32-packw-x8-gemm-goi-wasmsimd-u4.c src/x32-transposec/gen/x32-transposec-4x4-reuse-mov-wasmsimd.c src/x32-unpool/x32-unpool-wasmsimd.c src/x32-zip/x32-zip-x2-wasmsimd.c src/x32-zip/x32-zip-x3-wasmsimd.c src/x32-zip/x32-zip-x4-wasmsimd.c src/x32-zip/x32-zip-xm-wasmsimd.c src/xx-fill/xx-fill-wasmsimd-u64.c src/xx-pad/xx-pad-p16-wasmsimd-u16.c) SET(NON_PROD_WASMSIMD_MICROKERNEL_SRCS src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int16-u8.c src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int16-u24.c src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int16-u32.c src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int32-u8.c src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int32-u16.c src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int32-u24.c src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int32-u32.c src/f32-dwconv/gen/f32-dwconv-3f3m3l4c4s4r-minmax-wasmsimd-arm-acc2.c src/f32-dwconv/gen/f32-dwconv-3f3m3l4c4s4r-minmax-wasmsimd-x86-acc2.c src/f32-dwconv/gen/f32-dwconv-3f3m3l4c4s4r-minmax-wasmsimd-x86.c src/f32-dwconv/gen/f32-dwconv-3f3m3l4c4s4r-wasmsimd-acc2.c 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src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qs8-rdsum/gen/qs8-rdsum-7p7x-wasmsimd-c16.c src/qs8-rdsum/gen/qs8-rdsum-7p7x-wasmsimd-c64.c src/qs8-rsum/gen/qs8-rsum-wasmsimd-u8.c src/qs8-rsum/gen/qs8-rsum-wasmsimd-u16-acc2.c src/qs8-rsum/gen/qs8-rsum-wasmsimd-u32-acc2.c src/qs8-vadd/gen/qs8-vadd-minmax-wasmsimd-u8.c src/qs8-vadd/gen/qs8-vadd-minmax-wasmsimd-u16.c src/qs8-vadd/gen/qs8-vadd-minmax-wasmsimd-u24.c src/qs8-vaddc/gen/qs8-vaddc-minmax-wasmsimd-u8.c src/qs8-vaddc/gen/qs8-vaddc-minmax-wasmsimd-u16.c src/qs8-vaddc/gen/qs8-vaddc-minmax-wasmsimd-u24.c src/qs8-vcvt/gen/qs8-vcvt-wasmsimd-u8.c src/qs8-vcvt/gen/qs8-vcvt-wasmsimd-u32.c src/qs8-vlrelu/gen/qs8-vlrelu-wasmsimd-arm-u16.c src/qs8-vlrelu/gen/qs8-vlrelu-wasmsimd-x86-u8.c src/qs8-vlrelu/gen/qs8-vlrelu-wasmsimd-x86-u32.c src/qs8-vmul/gen/qs8-vmul-minmax-fp32-wasmsimd-mul32-ld64-u16.c src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-wasmsimd-mul32-ld64-u16.c src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c8s8r-minmax-fp32-wasmsimd-mul16.c src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c8s8r-minmax-fp32-wasmsimd-mul16.c src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c8s8r-minmax-fp32-wasmsimd-mul16.c src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c8s8r-minmax-fp32-wasmsimd-mul16.c src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c8s8r-minmax-fp32-wasmsimd-mul16.c src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c8s8r-minmax-fp32-wasmsimd-mul16.c src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-wasmsimd-mul16.c src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-wasmsimd-mul16.c src/qu8-f32-vcvt/gen/qu8-f32-vcvt-wasmsimd-u8.c src/qu8-f32-vcvt/gen/qu8-f32-vcvt-wasmsimd-u16.c src/qu8-f32-vcvt/gen/qu8-f32-vcvt-wasmsimd-u24.c src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-gemm/gen/qu8-gemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-gemm/gen/qu8-gemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-igemm/gen/qu8-igemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c src/qu8-igemm/gen/qu8-igemm-4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c src/qu8-rdsum/gen/qu8-rdsum-7p7x-wasmsimd-c16.c src/qu8-rdsum/gen/qu8-rdsum-7p7x-wasmsimd-c64.c src/qu8-rsum/gen/qu8-rsum-wasmsimd-u8.c src/qu8-rsum/gen/qu8-rsum-wasmsimd-u16-acc2.c src/qu8-rsum/gen/qu8-rsum-wasmsimd-u32-acc2.c src/qu8-vadd/gen/qu8-vadd-minmax-wasmsimd-u8.c src/qu8-vadd/gen/qu8-vadd-minmax-wasmsimd-u16.c src/qu8-vaddc/gen/qu8-vaddc-minmax-wasmsimd-u8.c src/qu8-vaddc/gen/qu8-vaddc-minmax-wasmsimd-u16.c src/qu8-vcvt/gen/qu8-vcvt-wasmsimd-u8.c src/qu8-vcvt/gen/qu8-vcvt-wasmsimd-u32.c src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-arm-u16.c src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-x86-u8.c src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-x86-u32.c src/qu8-vmul/gen/qu8-vmul-minmax-fp32-wasmsimd-mul32-ld64-u16.c src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-wasmsimd-mul32-ld64-u16.c src/s8-ibilinear/gen/s8-ibilinear-wasmsimd-dot16x2-c16.c src/s8-ibilinear/gen/s8-ibilinear-wasmsimd-mul32-c8.c src/s8-ibilinear/gen/s8-ibilinear-wasmsimd-mul32-c16.c src/u8-ibilinear/gen/u8-ibilinear-wasmsimd-dot16x2-c16.c src/u8-ibilinear/gen/u8-ibilinear-wasmsimd-mul32-c8.c src/u8-ibilinear/gen/u8-ibilinear-wasmsimd-mul32-c16.c src/x8-lut/gen/x8-lut-wasmsimd-u16.c src/x8-lut/gen/x8-lut-wasmsimd-u48.c src/x8-lut/gen/x8-lut-wasmsimd-u64.c src/x8-transposec/gen/x8-transposec-16x16-reuse-switch-wasmsimd.c src/x16-transposec/gen/x16-transposec-8x8-multi-mov-wasmsimd.c src/x16-transposec/gen/x16-transposec-8x8-multi-switch-wasmsimd.c src/x16-transposec/gen/x16-transposec-8x8-reuse-multi-wasmsimd.c src/x16-transposec/gen/x16-transposec-8x8-reuse-switch-wasmsimd.c src/x32-packw/gen/x32-packw-gio-wasmsimd-u2.c src/x32-packw/gen/x32-packw-x8s4-gemm-goi-wasmsimd-u4.c src/x32-packx/x32-packx-4x-wasmsimd.c src/x32-transposec/gen/x32-transposec-4x4-multi-mov-wasmsimd.c src/x32-transposec/gen/x32-transposec-4x4-multi-multi-wasmsimd.c src/x32-transposec/gen/x32-transposec-4x4-multi-switch-wasmsimd.c src/x32-transposec/gen/x32-transposec-4x4-reuse-multi-wasmsimd.c src/x32-transposec/gen/x32-transposec-4x4-reuse-switch-wasmsimd.c) SET(ALL_WASMSIMD_MICROKERNEL_SRCS ${PROD_WASMSIMD_MICROKERNEL_SRCS} + ${NON_PROD_WASMSIMD_MICROKERNEL_SRCS})