# Copyright 2022 Google LLC # # This source code is licensed under the BSD-style license found in the # LICENSE file in the root directory of this source tree. # # Description: microkernel filename lists for sse41 # # Auto-generated file. Do not edit! # Generator: tools/update-microkernels.py SET(PROD_SSE41_MICROKERNEL_SRCS src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int16-u16.c src/f32-f16-vcvt/gen/f32-f16-vcvt-sse41-u8.c src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-sse41-dup.c src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-sse41-dup.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-sse41-dup.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-sse41-dup.c src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse41-u32.c src/f32-vlrelu/gen/f32-vlrelu-sse41-u8.c src/f32-vrnd/gen/f32-vrndd-sse41-u8.c src/f32-vrnd/gen/f32-vrndne-sse41-u8.c src/f32-vrnd/gen/f32-vrndu-sse41-u8.c src/f32-vrnd/gen/f32-vrndz-sse41-u8.c src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-u8.c src/qd8-f32-qb4w-gemm/gen/qd8-f32-qb4w-gemm-1x4c8-minmax-sse41-ld128.c src/qd8-f32-qb4w-gemm/gen/qd8-f32-qb4w-gemm-3x4c8-minmax-sse41-ld128.c src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-sse41-ld64.c src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-sse41-ld64.c src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-1x4c8-minmax-sse41-ld64.c src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-4x4c8-minmax-sse41-ld64.c src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-sse41-mul16-add16.c src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-sse41-mul16-add16.c src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse41-u16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p8c-minmax-fp32-sse41-mul16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-sse41-mul16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-sse41-mul16.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-sse41-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-sse41-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-sse41-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-sse41-ld64.c src/qs8-rdsum/gen/qs8-rdsum-7p7x-minmax-fp32-sse41-c64.c src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul16-ld64-u8.c src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul16-ld64-u8.c src/qs8-vcvt/gen/qs8-vcvt-sse41-u32.c src/qs8-vlrelu/gen/qs8-vlrelu-sse41-u32.c src/qs8-vmul/gen/qs8-vmul-minmax-fp32-sse41-mul16-ld64-u16.c src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-sse41-mul16-ld64-u16.c src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-sse41-mul16.c src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-sse41-mul16.c src/qu8-f32-vcvt/gen/qu8-f32-vcvt-sse41-u16.c src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-sse41-ld64.c src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-sse41-ld64.c src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-sse41-ld64.c src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-sse41-ld64.c src/qu8-vadd/gen/qu8-vadd-minmax-sse41-mul16-ld64-u8.c src/qu8-vaddc/gen/qu8-vaddc-minmax-sse41-mul16-ld64-u8.c src/qu8-vcvt/gen/qu8-vcvt-sse41-u32.c src/qu8-vlrelu/gen/qu8-vlrelu-sse41-u32.c src/qu8-vmul/gen/qu8-vmul-minmax-fp32-sse41-mul16-ld64-u16.c src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-sse41-mul16-ld64-u16.c src/s8-ibilinear/gen/s8-ibilinear-sse41-c16.c src/s8-maxpool/s8-maxpool-9p8x-minmax-sse41-c16.c src/s8-vclamp/s8-vclamp-sse41-u64.c src/u8-ibilinear/gen/u8-ibilinear-sse41-c16.c) SET(NON_PROD_SSE41_MICROKERNEL_SRCS src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int16-u8.c src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int16-u24.c src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int16-u32.c src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int32-u8.c src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int32-u16.c src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int32-u24.c src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int32-u32.c src/f32-f16-vcvt/gen/f32-f16-vcvt-sse41-u16.c src/f32-f16-vcvt/gen/f32-f16-vcvt-sse41-u24.c src/f32-f16-vcvt/gen/f32-f16-vcvt-sse41-u32.c src/f32-qc4w-gemm/gen/f32-qc4w-gemm-3x8-minmax-sse41-dup.c src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x8-minmax-sse41-dup.c src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-sse41-dup.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-sse41-load1.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-sse41.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-sse41-dup.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-sse41-load1.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-minmax-sse41.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-minmax-sse41.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-sse41-load1.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-sse41.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-sse41-dup.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-sse41-load1.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-minmax-sse41.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x2c4-minmax-sse41.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-sse41-dup.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-sse41-load1.c src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-sse41.c src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse41-u8.c src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse41-u16.c src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse41-u24.c src/f32-vbinary/gen/f32-vprelu-sse41-u4.c src/f32-vbinary/gen/f32-vprelu-sse41-u8.c src/f32-vbinary/gen/f32-vpreluc-sse41-u4.c src/f32-vbinary/gen/f32-vpreluc-sse41-u8.c src/f32-vbinary/gen/f32-vrpreluc-sse41-u4.c src/f32-vbinary/gen/f32-vrpreluc-sse41-u8.c src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-u4.c src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-u8.c src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-u12.c src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-u16.c src/f32-velu/gen/f32-velu-sse41-rr2-p6-u4.c src/f32-velu/gen/f32-velu-sse41-rr2-p6-u8.c src/f32-velu/gen/f32-velu-sse41-rr2-p6-u12.c src/f32-velu/gen/f32-velu-sse41-rr2-p6-u16.c src/f32-vlrelu/gen/f32-vlrelu-sse41-u4.c src/f32-vrnd/gen/f32-vrndd-sse41-u4.c src/f32-vrnd/gen/f32-vrndne-sse41-u4.c src/f32-vrnd/gen/f32-vrndu-sse41-u4.c src/f32-vrnd/gen/f32-vrndz-sse41-u4.c src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-u4.c src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-u12.c src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-u16.c src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-u4.c src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-u8.c src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-u12.c src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-u16.c src/qd8-f32-qb4w-gemm/gen/qd8-f32-qb4w-gemm-1x4c8-minmax-sse41-ld64.c src/qd8-f32-qb4w-gemm/gen/qd8-f32-qb4w-gemm-2x4c8-minmax-sse41-ld64.c src/qd8-f32-qb4w-gemm/gen/qd8-f32-qb4w-gemm-2x4c8-minmax-sse41-ld128.c src/qd8-f32-qb4w-gemm/gen/qd8-f32-qb4w-gemm-3x4c8-minmax-sse41-ld64.c src/qd8-f32-qb4w-gemm/gen/qd8-f32-qb4w-gemm-4x4c8-minmax-sse41-ld64.c src/qd8-f32-qb4w-gemm/gen/qd8-f32-qb4w-gemm-4x4c8-minmax-sse41-ld128.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x4c8-minmax-sse41-ld64.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x4c8-minmax-sse41-ld128.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x4c8-minmax-sse41-madd-prfm.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x4c8-minmax-sse41-madd.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x4c8-minmax-sse41-ld64.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x4c8-minmax-sse41-ld128.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x4c8-minmax-sse41-madd-prfm.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x4c8-minmax-sse41-madd.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-3x4c8-minmax-sse41-ld64.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-3x4c8-minmax-sse41-ld128.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-3x4c8-minmax-sse41-madd-prfm.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-3x4c8-minmax-sse41-madd.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x4c8-minmax-sse41-ld64.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x4c8-minmax-sse41-ld128.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x4c8-minmax-sse41-madd-prfm.c src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x4c8-minmax-sse41-madd.c src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-sse41-ld128.c src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-sse41-ld64.c src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-sse41-ld128.c src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-sse41-ld64.c src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-sse41-ld128.c src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-sse41-ld128.c src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-1x4c8-minmax-sse41-ld128.c src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-2x4c8-minmax-sse41-ld64.c src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-2x4c8-minmax-sse41-ld128.c src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-3x4c8-minmax-sse41-ld64.c src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-3x4c8-minmax-sse41-ld128.c src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-4x4c8-minmax-sse41-ld128.c src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c4s4r-minmax-fp32-sse41-mul32.c src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-sse41-mul16-add16.c src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-sse41-mul16.c src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c4s4r-minmax-fp32-sse41-mul32.c src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-sse41-mul16-add16.c src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-sse41-mul16.c src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c4s4r-minmax-fp32-sse41-mul32.c src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-sse41-mul16-add16.c src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-sse41-mul16.c src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c4s4r-minmax-fp32-sse41-mul32.c src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-sse41-mul16-add16.c src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-sse41-mul16.c src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c4s4r-minmax-fp32-sse41-mul32.c src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-sse41-mul16-add16.c src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-sse41-mul16.c src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c4s4r-minmax-fp32-sse41-mul32.c src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-sse41-mul16-add16.c src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-sse41-mul16.c src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-sse41-mul16.c src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-sse41-mul32.c src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-sse41-mul16-add16.c src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-sse41-mul16.c src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-sse41-mul32.c src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-sse41-mul16.c src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-sse41-mul32.c src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-sse41-mul16-add16.c src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-sse41-mul16.c src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-sse41-mul32.c src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse41-u8.c src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse41-u24.c src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse41-u32.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c4s4r-minmax-fp32-sse41-mul32.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-sse41-mul16-add16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-sse41-mul16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c4s4r-minmax-fp32-sse41-mul32.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-sse41-mul16-add16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-sse41-mul16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c4s4r-minmax-fp32-sse41-mul32.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-sse41-mul16-add16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-sse41-mul16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c4s4r-minmax-fp32-sse41-mul32.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-sse41-mul16-add16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-sse41-mul16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c4s4r-minmax-fp32-sse41-mul32.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-sse41-mul16-add16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-sse41-mul16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c4s4r-minmax-fp32-sse41-mul32.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-sse41-mul16-add16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-sse41-mul16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-sse41-mul16-add16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-sse41-mul32.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-sse41-mul16-add16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-sse41-mul16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-sse41-mul32.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-sse41-mul16-add16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-sse41-mul32.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-sse41-mul16-add16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-sse41-mul16.c src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-sse41-mul32.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-sse41-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-sse41-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-sse41-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-sse41-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-sse41-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-sse41-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-sse41-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-sse41-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-sse41-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-sse41-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-sse41-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-sse41-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-sse41-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-sse41-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-sse41-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-sse41-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-sse41-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-sse41-ld128.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-sse41-ld64.c src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-sse41-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-sse41-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-sse41-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-sse41-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-sse41-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-sse41-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-sse41-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-sse41-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-sse41-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-sse41-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-sse41-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-sse41-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-sse41-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-sse41-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-sse41-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-sse41-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-sse41-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-sse41-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-sse41-ld128.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-sse41-ld64.c src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-sse41-ld128.c src/qs8-rdsum/gen/qs8-rdsum-7p7x-minmax-fp32-sse41-c16.c src/qs8-rdsum/gen/qs8-rdsum-7p7x-minmax-fp32-sse41-c32.c src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul16-ld64-u16.c src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul16-ld64-u24.c src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul16-ld64-u32.c src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul32-ld32-u8.c src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul32-ld32-u16.c src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul32-ld32-u24.c src/qs8-vadd/gen/qs8-vadd-minmax-sse41-mul32-ld32-u32.c src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul16-ld64-u16.c src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul16-ld64-u24.c src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul16-ld64-u32.c src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul32-ld32-u8.c src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul32-ld32-u16.c src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul32-ld32-u24.c src/qs8-vaddc/gen/qs8-vaddc-minmax-sse41-mul32-ld32-u32.c src/qs8-vcvt/gen/qs8-vcvt-sse41-u8.c src/qs8-vcvt/gen/qs8-vcvt-sse41-u16.c src/qs8-vlrelu/gen/qs8-vlrelu-sse41-u8.c src/qs8-vlrelu/gen/qs8-vlrelu-sse41-u16.c src/qs8-vmul/gen/qs8-vmul-minmax-fp32-sse41-mul16-ld64-u8.c src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-sse41-mul16-ld64-u8.c src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c4s4r-minmax-fp32-sse41-mul32.c src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c8s8r-minmax-fp32-sse41-mul16.c src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c4s4r-minmax-fp32-sse41-mul32.c src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c8s8r-minmax-fp32-sse41-mul16.c src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c4s4r-minmax-fp32-sse41-mul32.c src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c8s8r-minmax-fp32-sse41-mul16.c src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c4s4r-minmax-fp32-sse41-mul32.c src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c8s8r-minmax-fp32-sse41-mul16.c src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c4s4r-minmax-fp32-sse41-mul32.c src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c8s8r-minmax-fp32-sse41-mul16.c src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c4s4r-minmax-fp32-sse41-mul32.c src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c8s8r-minmax-fp32-sse41-mul16.c src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-sse41-mul32.c src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-sse41-mul16.c src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-sse41-mul32.c src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-sse41-mul32.c src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-sse41-mul16.c src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-sse41-mul32.c src/qu8-f32-vcvt/gen/qu8-f32-vcvt-sse41-u8.c src/qu8-f32-vcvt/gen/qu8-f32-vcvt-sse41-u24.c src/qu8-f32-vcvt/gen/qu8-f32-vcvt-sse41-u32.c src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-sse41-ld64.c src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-sse41-ld128.c src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-sse41-ld64.c src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-sse41-ld128.c src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-sse41-ld128.c src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-sse41-ld64.c src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-sse41-ld128.c src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-sse41-ld64.c src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-sse41-ld128.c src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-sse41-ld64.c src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-sse41-ld128.c src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-sse41-ld64.c src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-sse41-ld128.c src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-sse41-ld64.c src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-sse41-ld128.c src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-sse41-ld128.c src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-sse41-ld64.c src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-sse41-ld128.c src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-sse41-ld64.c src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-sse41-ld128.c src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-sse41-ld64.c src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-sse41-ld128.c src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-sse41-ld64.c src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-sse41-ld128.c src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-sse41-ld128.c src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-sse41-ld64.c src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-sse41-ld128.c src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-sse41-ld64.c src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-sse41-ld128.c src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-sse41-ld64.c src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-sse41-ld128.c src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-sse41-ld64.c src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-sse41-ld128.c src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-sse41-ld64.c src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-sse41-ld128.c src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-sse41-ld128.c src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-sse41-ld64.c src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-sse41-ld128.c src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-sse41-ld64.c src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-sse41-ld128.c src/qu8-vadd/gen/qu8-vadd-minmax-sse41-mul16-ld64-u16.c src/qu8-vadd/gen/qu8-vadd-minmax-sse41-mul32-ld32-u8.c src/qu8-vadd/gen/qu8-vadd-minmax-sse41-mul32-ld32-u16.c src/qu8-vaddc/gen/qu8-vaddc-minmax-sse41-mul16-ld64-u16.c src/qu8-vaddc/gen/qu8-vaddc-minmax-sse41-mul32-ld32-u8.c src/qu8-vaddc/gen/qu8-vaddc-minmax-sse41-mul32-ld32-u16.c src/qu8-vcvt/gen/qu8-vcvt-sse41-u8.c src/qu8-vcvt/gen/qu8-vcvt-sse41-u16.c src/qu8-vlrelu/gen/qu8-vlrelu-sse41-u8.c src/qu8-vlrelu/gen/qu8-vlrelu-sse41-u16.c src/qu8-vmul/gen/qu8-vmul-minmax-fp32-sse41-mul16-ld64-u8.c src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-sse41-mul16-ld64-u8.c src/s8-ibilinear/gen/s8-ibilinear-sse41-c8.c src/u8-ibilinear/gen/u8-ibilinear-sse41-c8.c src/x32-packw/gen/x32-packw-gio-sse41-u2.c) SET(ALL_SSE41_MICROKERNEL_SRCS ${PROD_SSE41_MICROKERNEL_SRCS} + ${NON_PROD_SSE41_MICROKERNEL_SRCS})