# Copyright 2022 Google LLC
#
# This source code is licensed under the BSD-style license found in the
# LICENSE file in the root directory of this source tree.
#
# Description: microkernel filename lists for armsimd32
#
# Auto-generated file. Do not edit!
#   Generator: tools/update-microkernels.py


SET(PROD_ARMSIMD32_MICROKERNEL_SRCS
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x2c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x2c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x2c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x2c4-minmax-fp32-armsimd32.c
  src/qs8-vcvt/gen/qs8-vcvt-armsimd32-u8.c
  src/qs8-vlrelu/gen/qs8-vlrelu-armsimd32-u4.c
  src/qu8-gemm/gen/qu8-gemm-1x2c4-minmax-fp32-armsimd32.c
  src/qu8-gemm/gen/qu8-gemm-2x2c4-minmax-fp32-armsimd32.c
  src/qu8-igemm/gen/qu8-igemm-1x2c4-minmax-fp32-armsimd32.c
  src/qu8-igemm/gen/qu8-igemm-2x2c4-minmax-fp32-armsimd32.c
  src/qu8-vcvt/gen/qu8-vcvt-armsimd32-u8.c
  src/qu8-vlrelu/gen/qu8-vlrelu-armsimd32-u4.c)

SET(NON_PROD_ARMSIMD32_MICROKERNEL_SRCS
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x1c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x1c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x1c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x1c4-minmax-fp32-armsimd32.c
  src/qs8-vcvt/gen/qs8-vcvt-armsimd32-u4.c
  src/qs8-vlrelu/gen/qs8-vlrelu-armsimd32-u8.c
  src/qu8-gemm/gen/qu8-gemm-1x1c4-minmax-fp32-armsimd32.c
  src/qu8-gemm/gen/qu8-gemm-2x1c4-minmax-fp32-armsimd32.c
  src/qu8-igemm/gen/qu8-igemm-1x1c4-minmax-fp32-armsimd32.c
  src/qu8-igemm/gen/qu8-igemm-2x1c4-minmax-fp32-armsimd32.c
  src/qu8-vcvt/gen/qu8-vcvt-armsimd32-u4.c
  src/qu8-vlrelu/gen/qu8-vlrelu-armsimd32-u8.c)

SET(ALL_ARMSIMD32_MICROKERNEL_SRCS ${PROD_ARMSIMD32_MICROKERNEL_SRCS} + ${NON_PROD_ARMSIMD32_MICROKERNEL_SRCS})